Continuous scaling of silicon-based metal oxide semiconductor field effect transistors (MOSFETs) has contributed to relentless advances in semiconductor technology. As the device scale approaches nanometer ranges, further scaling of semiconductor devices faces various challenges. Some challenges arise from the quantum mechanical nature of material properties at atomic dimensions such as gate tunneling current. Some other challenges arise from the stochastic nature of material properties such as fluctuations in dopant concentration on a microscopic scale, and resulting spread in threshold voltage and leakage current at semiconductor junctions. These and other challenges in semiconductor technology have renewed interest in semiconductor devices having non-conventional geometry.
A technology solution developed to enhance performance of complementary-metal-oxide-semiconductor (CMOS) devices and used extensively in advanced semiconductor devices is semiconductor on insulator (SOI) technology. While an SOI MOSFET typically offers advantages over a MOSFET with comparable dimensions and built on a bulk substrate by providing higher on current and lower parasitic capacitance between the body and other MOSFET components, the SOI MOSFET tends to have less consistency in the device operation due to “history effect” or “floating body effect”, in which the potential of the body, and subsequently the timing of the turn-on and the on-current of the SOI MOSFET are dependant on the past history of the SOI-MOSFET. Furthermore, the level of leakage current also depends on the voltage of the floating body which poses a challenge in the design of low power SOI MOSFET.
The body of an SOI MOSFET stores charge which is dependent on the history of the device, hence becoming a “floating” body. As such, SOI MOSFETs exhibit threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices.
The floating body effects in SOI MOSFETs are particularly a concern in applications such as static random access memory (SRAM) cells, in which threshold voltage (Vt) matching is extremely important as operating voltages continue to scale down. The floating body also poses leakage problems for pass-gate devices. Another exemplary semiconductor device in which the floating body effects are a concern is attacked SOI MOSFET structures, as used in logic gates, in which the conductive state of SOI MOSFET devices higher up in the stack are strongly influenced by stored body charge, resulting in reduced gate-to-source voltage overdrive available to these devices. Yet other exemplary semiconductor devices in which control of floating body is critical are sense amplifiers for SRAM circuits and current drives in a current minor circuit.
Another problem associated to SOI MOSFETs relate to self heating caused by high current flow due to the I2R law. Since the BOX has lower heat conductivity, the heat in the SOI continues to build causing a carrier to carrier scattering, which in turn leads drive current degradation.
In view of the above, a need exists for semiconductor devices capable of minimizing the floating body effect, the self heating effect in order to provide a consistent performance. Furthermore, there exists a need for a semiconductor structure that advantageously employs the floating body effect to perform a useful function and new methods of manufacturing the same. Additionally, there exists a need in industry for a semiconductor device capable of improving performance, by increasing, for example, the on current per unit device area over existing semiconductor devices.